Polysilicon (poly-Si) or amorphous silicon (a-Si) thin film transistors (TFTs) are typically utilized in the active pixel matrix and the peripheral circuits of large area, flat panel liquid crystal displays. Such TFT devices are particularly useful because of the compatibility of these devices with the glass substrate of the displays. Although both poly-Si and a-Si may be used in the fabrication of TFTs, the higher mobility of carriers in poly-Si TFTs, in comparison with a-Si TFTs, suggests that poly-Si TFTs most likely will be the choice for such flat panel displays for some time to come.
In general, TFTs are fabricated in the following manner. First, a low pressure chemical vapor deposition (LPCVD) is used to deposit an undoped a-Si layer upon a fused quartz substrate. The thickness of this a-Si layer is approximately 1000 .ANG.. The a-Si layer is then polycrystallized by heating the substrate and the a-Si layer to about 600.degree. C. in a nitrogen atmosphere. The crystalline silicon grain size in the polycrystalline or poly-Si layer, which results from this process, is typically about 0.2 .mu.m. Next, a 1000 .ANG. gate oxide layer and a 3500 .ANG. poly-Si gate electrode layer are LPCVD deposited upon this polycrystalline layer. Source/drain area and gate electrodes are then doped by self-aligned implantations. Finally, a 7000 .ANG. oxide layer is deposited by LPCVD.
The formation of the poly-Si layers results in the creation of grain boundary and intragranular defects which highly influence the characteristics of the devices fabricated by this process and result in a significant degradation in device performance. Recent studies have indicated that there are at least two types of trap states which result from these defects in poly-Si TFTs and which lead to the degradation of device performance. One type of trap state, near the midgap of the silicon band gap, is caused by the unpaired bonds which exist at each grain boundary. A second type of trap state, called a tail state, is caused by strained bonds within the poly-Si grains.
Although the mechanism is not well understood, passivation by hydrogenation during the fabrication process has been shown to reduce the density of these trap states and to improve device performance. Some experiments suggest that for poly-Si TFTs, the threshold voltage and subthreshold slope, which are most strongly affected by the density of midgap trap states caused by unpaired bonds at the grain boundaries, respond quickly to hydrogenation, while the leakage current and field-effect mobility, which are strongly affected by strained bond tail states, respond less quickly to hydrogenation.
For passivation by hydrogenation to remove the strained bond tail states, a higher hydrogen concentration is required than for the hydrogen passivation of the midgap trap states at the grain boundaries caused by dangling bonds. This result occurs because the number of strained bonds is roughly two orders of magnitude greater than the number of dangling bonds at a gain boundary.
Although several hydrogenation methods have been investigated to improve the quality of poly-Si TFTs, such methods have typically resulted in much longer processing times (up to 16 hours) with only a limited improvement to TFT quality.
For example, hydrogenation methods presently being attempted for poly-Si TFTs include immersing the poly-Si wafer in either a radio frequency (RF) parallel plate hydrogen plasma or an electron cyclotron resonance (ECR) microwave hydrogen plasma. Typically, an RF parallel plate hydrogen plasma treatment of the wafer requires a processing time in excess of 10 hours, while an ECR microwave hydrogen plasma treatment requires a processing time in excess of 2 hours.
Further, in addition to long processing times, these two hydrogen plasma approaches have resulted in only a limited improvement in the TFT devices. For example, 16 hours of RF plasma hydrogenation for a small grain size nMOS poly-Si TFT resulted in the following changes in the device parameters. The voltage at which the device turns on, V.sub.th, which should be as low as possible, showed only a 6 V decrease after hydrogenation. The field-effect mobility, .mu..sub.eff, which is the velocity at which the carrier (electron or hole) can move in device channel (which determines the gain of the device and hence the speed of the device and its drive capability) and which should be as large as possible, showed only a factor of 3 increase after hydrogenation. Finally, the subthreshold swing, S, which determines how fast a device can transition from its off state to its on state and which should be as small as possible, showed only a 1.0 V/decade decrease after hydrogenation.
The lack of improvement associated with these two approaches appears to result from the limited diffusion of hydrogen through the surface of the wafer; the small sheath potential which results in a low hydrogen ion current; and the accumulation of surface charge on the insulating substrate which contributes to preventing hydrogen ions from penetrating into the wafer. The typical substrate bias of hundreds of volts in the case of the RF parallel plate hydrogen plasma and tens of volts in the case of the ECR microwave hydrogen plasma are too low to accelerate enough hydrogen ions through the surface charge and into the device channels in the wafer.
Although the conventional technique of ion implantation can also, in principal, be used for hydrogenation, ion implantation typically has an extremely high cost and low efficiency due to the large size of the wafer being implanted and the resulting long times required to scan the wafer with the hydrogen ion beam. Further, ion beam implantation hydrogenation has not resulted in a significant improvement in TFT performance. This lack of improvement is possibly due to the fact that hydrogen ions cannot be directly sent to the device channel area through the gate oxide by ion beam implantation. The hydrogen ions cannot be directly implanted because to do so would result in damage to the gate oxide and the channel lattice and a low annealing temperature, which should be lower than the melting points of either the glass substrate or aluminum interconnection, cannot correct such lattice damage.
A way that has been attempted to avoid this problem is to adjust the hydrogen ion energy so as to send the hydrogen ions into the polysilicon gate layer while keeping away from the gate oxide layer. Because of the nonplanar structure of the device, ions implanted near the edge of the gate, that is, near the corners of the source or drain and channel, are closer to the channel area. This is due to the fact that the vertical distance to the surface at these locations is less than the vertical distance to the surface above the channel.
Following hydrogen ion implantation, post-implantation annealing is performed in an attempt to cover the whole channel through the lateral diffusion of the hydrogen ions. However, due to the vertical orientation of the ion beam used in implantation, the typical hydrogen ion dose (approximately 1.times.10.sup.17 /cm.sup.2) in the small area near the edge of gate may be not enough to passivate the whole channel. For example, the depth of penetration for a 10 keV hydrogen ion implantation for a silicon target is approximately 1500 .ANG.. However, the vertical distance between the device channel and the top of the TFT, for example, in one device is greater than 1.15 .mu.m (1000 .ANG. gate SiO.sub.2 +3500 .ANG. polysilicon gate+7000 .ANG. SiO.sub.2) . Thus, the shortest distance between the surface and the active channel is through an 8000 .ANG. SiO.sub.2 layer measured from the gate edges. Through this path, hydrogen may then reach the active channel by diffusing laterally. Thus, even with this reduced path length, a 100 keV hydrogen ion implantation is required to reach the active channel.
Finally, a pure diffusion process can not be used to passivate the defects. Although a pure diffusion process will not damage the devices, as the hydrogen implantation just discussed will, a pure diffusion process operating at 300.degree.-400.degree. C. cannot bring enough hydrogen ions (up to a 1.times.10.sup.17 /cm.sup.2 dose being required) to the device channel except after very long periods of exposure. The long times required for pure diffusion to bring a sufficient number of hydrogen ions to the device channel make such a process unacceptable for manufacturing purposes.
Thus, a hydrogenation process is desired which will not damage the devices on the wafer and yet will not require the long exposure times typical of diffusion processes.